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FEATURES Enhanced Replacements for LF412 and TL082 AC PERFORMANCE Settles to 0.01% in 1.0 ms 16 V/ s min Slew Rate (AD712J) 3 MHz min Unity Gain Bandwidth (AD712J) DC PERFORMANCE 0.30 mV max Offset Voltage: (AD712C) 5 V/ C max Drift: (AD712C) 200 V/mV min Open-Loop Gain (AD712K) 4 V p-p max Noise, 0.1 Hz to 10 Hz (AD712C) Surface Mount Available in Tape and Reel in Accordance with EIA-481A Standard MIL-STD-883B Parts Available Single Version Available: AD711 Quad Version: AD713 Available in Plastic Mini-DIP, Plastic SOIC, Hermetic Cerdip, Hermetic Metal Can Packages and Chip Form PRODUCT DESCRIPTION
Dual Precision, Low Cost, High Speed, BiFET Op Amp AD712
CONNECTION DIAGRAMS TO-99 (H) Package
AMPLIFIER NO. 1 OUTPUT INVERTING OUTPUT NONINVERTING OUTPUT +VS AMPLIFIER NO. 2
OUTPUT INVERTING INPUT
AD712
-VS
NONINVERTING INPUT
Plastic Mini-DIP (N) Package SOIC (R) Package and Cerdip (Q) Package
AMPLIFIER NO. 1 OUTPUT 1 INVERTING 2 OUTPUT NONINVERTING 3 OUTPUT V- 4 AMPLIFIER NO. 2
8 7 6
V+ OUTPUT
AD712
INVERTING INPUT NONINVERTING 5 INPUT
The AD712 is a high speed, precision monolithic operational amplifier offering high performance at very modest prices. Its very low offset voltage and offset voltage drift are the results of advanced laser wafer trimming technology. These performance benefits allow the user to easily upgrade existing designs that use older precision BiFETs and, in many cases, bipolar op amps. The superior ac and dc performance of this op amp makes it suitable for active filter applications. With a slew rate of 16 V/s and a settling time of 1 s to 0.01%, the AD712 is ideal as a buffer for 12-bit D/A and A/D Converters and as a high-speed integrator. The settling time is unmatched by any similar IC amplifier. The combination of excellent noise performance and low input current also make the AD712 useful for photo diode preamps. Common-mode rejection of 88 dB and open loop gain of 400 V/mV ensure 12-bit performance even in high-speed unity gain buffer circuits. The AD712 is pinned out in a standard op amp configuration and is available in seven performance grades. The AD712J and AD712K are rated over the commercial temperature range of 0C to +70C. The AD712A, AD712B and AD712C are rated over the industrial temperature range of -40C to +85C. The AD712S and AD712T are rated over the military temperature range of -55C to +125C and are available processed to MILSTD-883-B, Rev. C. Extended reliability PLUS screening is available, specified over the commercial and industrial temperature ranges. PLUS REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
screening includes 168-hour burn-in, as well as other environmental and physical tests. The AD712 is available in an 8-lead plastic mini-DIP, SOIC, cerdip, TO-99 metal can, or in chip form.
PRODUCT HIGHLIGHTS
1. The AD712 offers excellent overall performance at very competitive prices. 2. Analog Devices' advanced processing technology and with 100% testing guarantees a low input offset voltage (0.3 mV max, C grade, 3 mV max, J grade). Input offset voltage is specified in the warmed-up condition. Analog Devices' laser wafer drift trimming process reduces input offset voltage drifts to 5 V/C max on the AD712C. 3. Along with precision dc performance, the AD712 offers excellent dynamic response. It settles to 0.01% in 1 s and has a minimum slew rate of 16 V/s. Thus this device is ideal for applications such as DAC and ADC buffers which require a combination of superior ac and dc performance. 4. The AD712 has a guaranteed and tested maximum voltage noise of 4 V p-p, 0.1 Hz to 10 Hz (AD712C). 5. Analog Devices' well-matched, ion-implanted JFETs ensure a guaranteed input bias current (at either input) of 50 pA max (AD712C) and an input offset current of 10 pA max (AD712C). Both input bias current and input offset current are guaranteed in the warmed-up condition.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD712-SPECIFICATIONS (V =
S
15 V @ TA = +25 C unless otherwise noted)
Min AD712K/B/T Typ 0.2 7 100 15 Max 1.0/0.7/0.7 2.0/1.5/1.5 10 86 86 Min AD712C Typ 0.1 3 110 15 75 1.7/4.8/77 100 25 0.6/1.6/26 1.0/0.7/0.7 2.0/1.5/1.5 10 25 120 90 3.4 18 4.0 200 20 1.0 0.0003 3 x 1012 5.5 3 x 1012 5.5 20 +14.5, -11.5 3.4 18 1.2 120 90 4.0 200 20 1.0 0.0003 3 x 1012 5.5 3 x 1012 5.5 20 +14.5, -11.5 +VS - 2 -VS + 4 20 1.3 50 3.2 75 10 0.7 0.3 0.6 5 10 Max 0.3 0.6 5 Units mV mV V/C dB dB V/Month pA nA pA pA nA mV mV V/C pA dB dB MHz kHz V/s s % pF pF V +VS - 2 V
Parameter
Min
AD712J/A/S Typ 0.3 7 95 15 25 0.6/1.6/26
Max 3/1/1 4/2/2 20/20/20
INPUT OFFSET VOLTAGE1 Initial Offset TMIN to TMAX vs. Temp vs. Supply 76 TMIN to TMAX 76/76/76 Long-Term Offset Stability INPUT BIAS CURRENT2 VCM = 0 V VCM = 0 V @ TMAX VCM = 10 V INPUT OFFSET CURRENT VCM = 0 V VCM = 0 V @ TMAX MATCHING CHARACTERISTICS Input Offset Voltage TMIN to TMAX Input Offset Voltage Drift Input Bias Current Crosstalk @ f = 1 kHz @ f = 100 kHz FREQUENCY RESPONSE Small Signal Bandwidth Full Power Response Slew Rate Settling Time to 0.01% Total Harmonic Distortion INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE RANGE Differential3 Common-Mode Voltage4 TMIN to TMAX Common-Mode Rejection Ratio VCM = 10 V TMIN to TMAX VCM = 11 V TMIN to TMAX INPUT VOLTAGE NOISE 3.0 16
80 80
75 1.7/4.8/77 100 25 0.6/1.6/26 3/1/1 4/2/2 20/20/20 25
20 0.5/1.3/20
10 0.3/0.7/11
5 0.1/0.3/5
5 0.3
120 90 4.0 200 20 1.0 0.0003 3 x 1012 5.5 3 x 1012 5.5 20 +14.5, -11.5
1.2
1.2
-VS + 4
+VS - 2
-VS + 4
76 76/76/76 70 70/70/70
88 84 84 80 2 45 22 18 16 0.01
80 80 76 74
88 84 84 80 2 45 22 18 16 0.01
86 86 76 74
94 90 90 84 2 45 22 18 16 0.01
dB dB dB dB V p-p nV/Hz nV/Hz nV/Hz nV/Hz pA/Hz V/mV V/mV V V mA V V mA
INPUT CURRENT NOISE OPEN-LOOP GAIN
150 400 100/100/100
200 100
400
200 100
400
OUTPUT CHARACTERISTICS Voltage +13, -12.5 +13.9, -13.3 12/ 12/ 12 +13.8, -13.1 Current 25 POWER SUPPLY Rated Performance Operating Range Quiescent Current 15 4.5 5.0 18 6.8
+13, -12.5 +13.9, -13.3 12 +13.8, -13.1 25 15 4.5 5.0 18 6.0
+13, -12.5 +13.9, -13.3 12 +13.8, -13.1 25 15 4.5 5.0 18 5.6
NOTES 1 Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T A = +25C. 2 Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25C. For higher temperatures, the current doubles every 10C. 3 Defined as voltage between inputs, such that neither exceeds 10 V from ground. 4 Typically exceeding -14.1 V negative common-mode voltage on either input results in an output phase reversal. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. Specifications subject to change without notice.
-2-
REV. B
AD712
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation2 Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and -VS Storage Temperature Range (Q, H) . . . . . . . -65C to +150C Storage Temperature Range (N, R) . . . . . . . . -65C to +125C Operating Temperature Range AD712J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C AD712A/B/C . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C AD712S/T . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 8-Lead Plastic Package: JA = 165C/Watt 8-Lead Cerdip Package: JC = 22C/Watt; JA = 110C/Watt 8-Lead Metal Can Package: JC = 65C/Watt; JA = 150C/Watt 8-Lead SOIC Package: JA = 100C 3 For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage.
ORDERING GUIDE
Model AD712ACHIPS AD712AH AD712AQ AD712BH AD712BQ AD712CH AD712CN AD712JN AD712JR AD712JR-REEL AD712JR-REEL7 AD712KN AD712KR AD712KR-REEL AD712KR-REEL7 AD712SCHIPS AD712SQ AD712SQ/883B AD712TQ AD712TQ/883B Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -55C to +125C -55C to +125C -55C to +125C -55C to +125C -55C to +125C Package Description Bare Die 8-Lead Metal Can 8-Lead Ceramic DIP 8-Lead Metal Can 8-Lead Ceramic DIP 8-Lead Metal Can 8-Lead Plastic DIP 8-Lead Plastic DIP 8-Lead Plastic SOIC 8-Lead Plastic SOIC 8-Lead Plastic SOIC 8-Lead Plastic DIP 8-Lead Plastic SOIC 8-Lead Plastic SOIC 8-Lead Plastic SOIC Bare Die 8-Lead Ceramic DIP 8-Lead Ceramic DIP 8-Lead Ceramic DIP 8-Lead Ceramic DIP Package Option H-08A Q-8 H-08A Q-8 H-08A N-8 N-8 R-8 R-8 R-8 N-8 R-8 R-8 R-8 Q-8 Q-8 Q-8 Q-8
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm). Contact factory for latest dimensions.
REV. B
-3-
AD712-Typical Performance Characteristics
20 20
OUTPUT VOLTAGE SWING - Volts p-p
30
OUTPUT VOLTAGE SWING - Volts
INPUT VOLTAGE SWING - Volts
25
15
15 +VOUT 10
20 15V SUPPLIES 15
10 RL = 2k 25 C 5
-VOUT RL = 2k 25 C
10
5
5
0
0
10 5 SUPPLY VOLTAGE
15 Volts
20
0
0
10 5 SUPPLY VOLTAGE
15 Volts
20
0 10
100 1k LOAD RESISTANCE -
10k
Figure 1. Input Voltage Swing vs. Supply Voltage
Figure 2. Output Voltage Swing vs. Supply Voltage
Figure 3. Output Voltage Swing vs. Load Resistance
6
INPUT BIAS CURRENT (VCM = 0) - Amps
106 107 108 109 1010 1011 1012 -60 -40 -40
OUTPUT IMPEDANCE -
100
QUIESCENT CURRENT - mA
5
10
4
1.0
3
0.1
2
0
10 5 SUPPLY VOLTAGE
15 Volts
20
0 20 40 60 80 100 120 140 TEMPERATURE - C
0.01 1k
10k
100k 1M FREQUENCY - Hz
10M
Figure 4. Quiescent Current vs. Supply Voltage
Figure 5. Input Bias Current vs. Temperature
Figure 6. Output Impedance vs. Frequency
100
26 SHORT CIRCUIT CURRENT LIMIT - mA UNITY GAIN BANDWIDTH - MHz 24 + OUTPUT CURRENT 22 20 18 - OUTPUT CURRENT 16 14 12 10 -60 -40 -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE - C
5.0
INPUT BIAS CURRENT - pA
MAX J GRADE LIMIT 75 VS = +15V 25 C 50
4.5
4.0
25
3.5
0 -10
0 5 -5 COMMON MODE VOLTAGE - Volts
10
3.0 -60 -40 -20
0 20 40 60 80 100 120 140 TEMPERATURE - C
Figure 7. Input Bias Current vs. Common Mode Voltage
Figure 8. Short Circuit Current Limit vs. Temperature
Figure 9. Unity Gain Bandwidth vs. Temperature
-4-
REV. B
AD712
100 80
OPEN LOOP GAIN - dB
100 80
OPEN LOOP GAIN - dB
PHASE MARGIN - C
125
110
120
POWER SUPPLY REJECTION - dB
100
+ SUPPLY
80
60 40 GAIN PHASE 2k 100pF LOAD
60 40
115 RL = 2k 25 C
60 - SUPPLY VS = 15V SUPPLIES WITH 1V p-p SINE WAVE 25 C
110 105
40
20
20
0 -20 10
0 -20 10M
100 95 0 5 10 SUPPLY VOLTAGE 15 Volts 20
20
100
1k 10k 100k FREQUENCY - Hz
1M
0 10 100 1k 10k 100k 1M SUPPLY MODULATION FREQUENCY - Hz
Figure 10. Open-Loop Gain and Phase Margin vs. Frequency
Figure 11. Open-Loop Gain vs. Supply Voltage
Figure 12. Power Supply Rejection vs. Frequency
100 OUTPUT VOLTAGE - Volts p-p
30 VOLTS OUTPUT SWING FROM 0V TO RL = 2k 25 C VS = 15V
10 8 6 4 2 0 -2 -4 -6 -8 -10 0.5 0.6 0.7 0.8 0.9 SETTLING TIME - s 1.0 ERROR 1% 0.1% 0.01% 1% 0.1% 0.01%
80 VS = 15V VCM = 1Vp-p 25 C
25
20
CMR - dB
60
15
40
10
20
5 0 100k
0 10
100
1k 10k 100k FREQUENCY - Hz
1M
1M INPUT FREQUENCY - Hz
10M
Figure 13. Common Mode Rejection vs. Frequency
Figure 14. Large Signal Frequency Response
Figure 15. Output Swing and Error vs. Settling Time
-70
1k
25
-80 3V RMS RL = 2k CL = 100pF
INPUT NOISE VOLTAGE - nV/ Hz
20
100
-90
SLEW RATE - V/ s
1 10 100 1k FREQUENCY - Hz 10k 100k
THD - dB
15
-100
10
-110
10
5
-120 -130 100
1
1k 10k FREQUENCY - Hz 100k
0
0
100 200 300 400 500 600 700 800 900 INPUT ERROR SIGNAL - mV (AT SUMMING JUNCTION)
Figure 16. Total Harmonic Distortion vs. Frequency
Figure 17. Input Noise Voltage Spectral Density
Figure 18. Slew Rate vs. Input Error Signal
REV. B
-5-
AD712
25
+VS 0.1 F
SLEW RATE - V/ s
INPUT
1/2 AD712
2k 0.1 F
OUTPUT 100pF
20
-VS
Figure 20. T.H.D. Test Circuit
VOUT
15 -60
-40
-20
0
20 40 60 80 TEMPERATURE - C
100
120
140
2
+VS 8 1 5k VOUT 10VIN 7 5k
20k 6
2.2k
Figure 19. Slew Rate vs. Temperature
20V p-p VIN
1/2 AD712 3
1/2 AD712 5
4 -VS
CROSSTALK = 20 LOG
Figure 21. Crosstalk Test Circuit
100
100 90
+VS 0.1 F
90
1/2 AD712
VIN 0.1 F SQUARE WAVE INPUT
VOUT
10
10 0%
RL 2k
CL 100pF
0%
5V
1s
50mV
100ns
-VS
Figure 22a. Unity Gain Follower
Figure 22b. Unity Gain Follower Pulse Response (Large Signal)
Figure 22c. Unity Gain Follower Pulse Response (Small Signal)
5k +VS 0.1 F 5k
100 90
100 90
VIN
1/2 AD712
SQUARE WAVE INPUT -VS 0.1 F
VOUT
10
10 0%
RL 2k
CL 100pF
0%
5V
1s
50mV
200ns
Figure 23a. Unity Gain Inverter
Figure 23b. Unity Gain Inverter Pulse Response (Large Signal)
Figure 23c. Unity Gain Inverter Pulse Response (Small Signal)
-6-
REV. B
AD712
OPTIMIZING SETTLING TIME
Most bipolar high-speed D/A converters have current outputs; therefore, for most applications, an external op amp is required for current-to-voltage conversion. The settling time of the converter/op amp combination depends on the settling time of the DAC and output amplifier. A good approximation is:
t S Total = (t S DAC )2 + (t S AMP )2
In addition to a significant improvement in settling time, the low offset voltage, low offset voltage drift, and high open-loop gain of the AD711/AD712 family assures 12-bit accuracy over the full operating temperature range. The excellent high-speed performance of the AD712 is shown in the oscilloscope photos of Figure 25. Measurements were taken using a low input capacitance amplifier connected directly to the summing junction of the AD712 - both photos show the worst case situation: a full-scale input transition. The DAC's 4 k [10 k||8 k = 4.4 k] output impedance together with a 10 k feedback resistor produce an op amp noise gain of 3.25. The current output from the DAC produces a 10 V step at the op amp output (0 to -10 V Figure 25a, -10 V to 0 V Figure 25b.) Therefore, with an ideal op amp, settling to 1/2 LSB ( 0.01%) requires that 375 V or less appears at the summing junction. This means that the error between the input and output (that voltage which appears at the AD712 summing junction) must be less than 375 V. As shown in Figure 25, the total settling time for the AD712/AD565 combination is 1.2 microseconds.
The settling time of an op amp DAC buffer will vary with the noise gain of the circuit, the DAC output capacitance, and with the amount of external compensation capacitance across the DAC output scaling resistor. Settling time for a bipolar DAC is typically 100 ns to 500 ns. Previously, conventional op amps have required much longer settling times than have typical state-of-the-art DACs; therefore, the amplifier settling time has been the major limitation to a high-speed voltage-output D-to-A function. The introduction of the AD711/AD712 family of op amps with their 1 s (to 0.01% of final value) settling time now permits the full high-speed capabilities of most modern DACs to be realized.
0.1 F BIPOLAR OFFSET ADJUST REF OUT + 10V - REF IN 19.95k 0.5mA IREF REF GND R1 100 BIPOLAR OFF
R2 GAIN 100 ADJUST
VCC
20V SPAN 5k
AD565A
9.95k 5k
10V SPAN DAC OUT
10pF
+15V 0.1 F
DAC
20k IOUT = 4 IREF CODE
IO
8k
1/2 AD712
0.1 F
OUTPUT -10V TO +10V
-VEE 0.1 F
POWER GND
MSB
LSB
-15V
Figure 24. 10 V Voltage Output Bipolar DAC
1mV
100 90
5V
100 90
1mV
5V
SUMMING JUNCTION
SUMMING JUNCTION
0V
10 0%
0V
OUTPUT
-10V
10 0%
OUTPUT
-10V
500ns
500ns
a. (Full-Scale Negative Transition)
b. (Full-Scale Positive Transition)
Figure 25. Settling Characteristics for AD712 with AD565A
REV. B
-7-
AD712
OP AMP SETTLING TIME A MATHEMATICAL MODEL
The design of the AD712 gives careful attention to optimizing individual circuit components; in addition, a careful trade-off was made: the gain bandwidth product (4 MHz) and slew rate (20 V/s) were chosen to be high enough to provide very fast settling time but not too high to cause a significant reduction in phase margin (and therefore stability). Thus designed, the AD712 settles to 0.01%, with a 10 V output step, in under 1 s, while retaining the ability to drive a 250 pF load capacitance when operating as a unity gain follower. If an op amp is modeled as an ideal integrator with a unity gain crossover frequency of /2, Equation 1 will accurately describe the small signal behavior of the circuit of Figure 26a, consisting of an op amp connected as an I-to-V converter at the output of a bipolar or CMOS DAC. This equation would completely describe the output of the system if not for the op amp's finite slew rate and other nonlinear effects. Equation 1.
VO -R = I IN R(C f = CX ) 2 GN s + + RC f s + 1
When RO and IO are replaced with their Thevenin VIN and RIN equivalents, the general purpose inverting amplifier of Figure 26b is created. Note that when using this general model, capacitance CX is EITHER the input capacitance of the op amp if a simple inverting op amp is being simulated OR it is the combined capacitance of the DAC output and the op amp input if the DAC buffer is being modeled.
1/2 AD712
RL CF RIN VIN CX R CL
VOUT
Figure 26b. Simplified Model of the AD712 Used as an Inverter
where 2 =op amp's unity gain frequency GN = "noise" gain of circuit 1 + R O This equation may then be solved for Cf: Equation 2.
Cf = 2 - GN 2 RC X + (1 - GN ) + R R
R
In either case, the capacitance CX causes the system to go from a one-pole to a two-pole response; this additional pole increases settling time by introducing peaking or ringing in the op amp output. Since the value of CX can be estimated with reasonable accuracy, Equation 2 can be used to choose a small capacitor, CF, to cancel the input pole and optimize amplifier response. Figure 27 is a graphical solution of Equation 2 for the AD712 with R = 4 k.
60
50
In these equations, capacitor CX is the total capacitor appearing the inverting terminal of the op amp. When modeling a DAC buffer application, the Norton equivalent circuit of Figure 26a can be used directly; capacitance CX is the total capacitance of the output of the DAC plus the input capacitance of the op amp (since the two are in parallel).
40
GN = 4.0
CX
30
GN = 3.0 GN = 2.0
20 GN = 1.5 10 GN = 1.0
0
1/2 AD712
RL CF R IO RO CX CL
0
VOUT
10
20
30 CF
40
50
60
Figure 27. Value of Capacitor CF vs. Value of CX
Figure 26a. Simplified Model of the AD712 Used as a Current-Out DAC Buffer
-8-
REV. B
AD712
The photos of Figures 28a and 28b show the dynamic response of the AD712 in the settling test circuit of Figure 29. The input of the settling time fixture is driven by a flat-top pulse generator. The error signal output from the false summing node of A1 is clamped, amplified by A2 and then clamped again. The error signal is thus clamped twice: once to prevent overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope preamp type 7A26 was carefully chosen because it does not overload with these input levels. Amplifier A2 needs to be a very high speed FET-input op amp; it provides a gain of 10, amplifying the error signal output of A1.
GUARDING
5mV 500ns
5V
100 90
10 0%
Figure 28a. Settling Characteristics 0 V to +10 V Step Upper Trace: Output of AD712 Under Test (5 V/Div) Lower Trace: Amplified Error Voltage (0.01%/Div)
5V
100 90
The low input bias current (15 pA) and low noise characteristics of the AD712 BiFET op amp make it suitable for electrometer applications such as photo diode preamplifiers and picoampere current-to-voltage converters. The use of a guarding technique such as that shown in Figure 30, in printed circuit board layout and construction is critical to minimize leakage currents. The guard ring is connected to a low impedance potential at the same level as the inputs. High impedance signal lines should not be extended for any unnecessary length on the printed circuit board.
TO-99 (H) PACKAGE
4
PLASTIC MINI-DIP (N) PACKAGE CERDIP (Q) PACKAGE AND SOIC (R) PACKAGE
4 5 6 6 3 2 7 8
10 0%
5 3
5mV
500ns
2
Figure 28b. Settling Characteristics 0 V to -10 V Step Upper Trace: Output of AD712 Under Test (5 V/Div) Lower Trace: Amplified Error Voltage (0.01%/Div)
1 8
7
1
Figure 30. Board Layout for Guarding Inputs
5pF
HP2835
1/2 AD712
205
VERROR
5
TEKTRONIX 7A26 OSCILLOSCOPE PREAMP INPUT SECTION
1M HP2835 0.47 F 4.99k DATA DYNAMICS 5109 VIN 200 10k 1.1k 10k 0.2-0.6pF 4.99k 5-18pF -15V +15V 10k 0.47 F
20pF
1/2 AD712
(OR EQUIVALENT FLAT TOP PULSE GENERATION) 5k 0.1 F 0.1 F
VOUT 10pF
-15V +15V
Figure 29. Settling Time Test Circuit
REV. B
-9-
AD712
D/A CONVERTER APPLICATIONS
VDD R2A* C1A 33pF VDD VREF R1A* *REFER TO TABLE I DB11-DB0 RFB OUT1 VIN +15V 0.1 F
The AD712 is an excellent output amplifier for CMOS DACs. It can be used to perform both 2 quadrant and 4 quadrant operation. The output impedance of a DAC using an inverted R-2R ladder approaches R for codes containing many 1s, 3R for codes containing a single 1, and for codes containing all zero, the output impedance is infinite. For example, the output resistance of the AD7545 will modulate between 11 k and 33 k. Therefore, with the DAC's internal feedback resistance of 11 k, the noise gain will vary from 2 to 4/3. This changing noise gain modulates the effect of the input offset voltage of the amplifier, resulting in nonlinear DAC amplifier performance. The AD712K with guaranteed 700 V offset voltage minimizes this effect to achieve 12-bit performance. Figures 31 and 32 show the AD712 and AD7545 (12-bit CMOS DAC) configured for unipolar binary (2-quadrant multiplication) or bipolar (4-quadrant multiplication) operation. Capacitor C1 provides phase compensation to reduce overshoot and ringing.
GAIN ADJUST
AD7545
AGND DGND ANALOG COMMON
1/2 AD712
VOUTA
VDD
R2B* C1B 33pF
GAIN ADJUST VIN R1B* *REFER TO TABLE I
VDD VREF
RFB OUT1
AD7545
AGND DGND ANALOG COMMON
1/2 AD712
0.1 F
VOUTB
-15V DB11-DB0
Figure 31. Unipolar Binary Operation
R1 and R2 calibrate the zero offset and gain error of the DAC. Specific values for these resistors depend upon the grade of AD7545 and are shown below.
Table I. Recommended Trim Resistor Values vs. Grades of the AD7545 for VDD = +5 V
Trim Resistor JN/AQ/SD KN/BQ/TD LN/UD GLN/GUD
R1 R2
500 150
200 68
100 33
20 6.8
VDD
R2* C1 33pF +15V 0.1 F
R4 20k
1% R5 20k 1%
GAIN ADJUST VIN R1*
VDD VREF
RFB OUT1
AD7545
AGND DGND
1/2 AD712
R3 10k 1%
1/2 AD712
0.1 F
VOUT
DB11-DB0 12 DATA INPUT *FOR VALUES OF R1 AND R2 SEE TABLE I
ANALOG COMMON
-15V
Figure 32. Bipolar Operation
-10-
REV. B
AD712
Figures 33a and 33b show the settling time characteristics of the AD712 when used as a DAC output buffer for the AD7545.
DRIVING THE ANALOG INPUT OF AN A/D CONVERTER
100 90
10 0%
500ns
An op amp driving the analog input of an A/D converter, such as that shown in Figure 34, must be capable of maintaining a constant output voltage under dynamically changing load conditions. In successive-approximation converters, the input current is compared to a series of switched trial currents. The comparison point is diode clamped but may deviate several hundred millivolts resulting in high frequency modulation of A/D input current. The output impedance of a feedback amplifier is made artificially low by the loop gain. At high frequencies, where the loop gain is low, the amplifier output impedance can approach its open loop value. Most IC amplifiers exhibit a minimum open loop output impedance of 25 due to current limiting resistors.
12/8 CS AO STS HIGH BITS
a. Full-Scale Positive Transition
100 90
GAIN ADJUST
R/C CE
AD574
MIDDLE BITS LOW BITS +5V
REF IN R2 100 +15V 0.1 F
10 0%
R1 100
REF OUT BIP OFF 10VIN 20VIN ANA COM
500ns
b. Full-Scale Negative Transition Figure 33. Settling Characteristics for AD712 with AD7545
NOISE CHARACTERISTICS
10V ANALOG INPUT
1/2 AD712
0.1 F
OFFSET ADJUST
+15V -15V DIG COM
-15V
ANALOG COM
Figure 34. AD712 as ADC Unity Gain Buffer
The random nature of noise, particularly in the 1/f region, makes it difficult to specify in practical terms. At the same time, designers of precision instrumentation require certain guaranteed maximum noise levels to realize the full accuracy of their equipment. The AD712C grade is specified at a maximum level of 4.0 V p-p, in a 0.1 Hz to 10 Hz bandwidth. Each AD712C receives a 100% noise test for two 10-second intervals; devices with any excursion in excess of 4.0 V are rejected. The screened lot is then submitted to Quality Control for verification on an AQL basis. All other grades of the AD712 are sample-tested on an AQL basis to a limit of 6 V p-p, 0.1 Hz to 10 Hz.
A few hundred microamps reflected from the change in converter loading can introduce errors in instantaneous input voltage. If the A/D conversion speed is not excessive and the bandwidth of the amplifier is sufficient, the amplifier's output will return to the nominal value before the converter makes its comparison. However, many amplifiers have relatively narrow bandwidth yielding slow recovery from output transients. The AD712 is ideally suited to drive high speed A/D converters since it offers both wide bandwidth and high open-loop gain.
REV. B
-11-
AD712
PD711 BUFF
100 90 100 90
5V
1s
10 0%
10 0%
500mV -10V ADC IN
200ns
a. Source Current = 2 mA
Figure 37. Transient Response RL = 2 k, CL = 500 pF
ACTIVE FILTER APPLICATIONS
PD711 BUFF
100 90
10 0%
In active filter applications using op amps, the dc accuracy of the amplifier is critical to optimal filter performance. The amplifier's offset voltage and bias current contribute to output error. Offset voltage will be passed by the filter and may be amplified to produce excessive output offset. For low frequency applications requiring large value input resistors, bias currents flowing through these resistors will also generate an offset voltage.
200ns
500mV
-5V ADC IN
b. Sink Current = 1 mA Figure 35. ADC Input Unity Gain Buffer Recovery Times
In addition, at higher frequencies, an op amp's dynamics must be carefully considered. Here, slew rate, bandwidth, and open-loop gain play a major role in op amp selection. The slew rate must be fast as well as symmetrical to minimize distortion. The amplifier's bandwidth in conjunction with the filter's gain will dictate the frequency response of the filter. The use of a high performance amplifier such as the AD712 will minimize both dc and ac errors in all active filter applications.
The circuit in Figure 36 employs a 100 isolation resistor which enables the amplifier to drive capacitive loads exceeding 1500 pF; the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. Low frequency feedback is returned to the amplifier summing junction via the low pass filter formed by the 100 series resistor and the load capacitance, CL. Figure 37 shows a typical transient response for this connection.
4.99k 30pF +VIN 0.1 F +- 4.99k INPUT TYPICAL CAPACITANCE LIMIT FOR VARIOUS LOAD RESISTORS R1 2k 10k 20 C1 UP TO 1500pF 1500pF 1000pF -VIN
DRIVING A LARGE CAPACITIVE LOAD
1/2 AD712
0.1 F -+
100 C1 R1
OUTPUT
Figure 36. Circuit for Driving a Large Capacitive Load
-12-
REV. B
AD712
SECOND ORDER LOW PASS FILTER
Figure 38 depicts the AD712 configured as a second order Butterworth low pass filter. With the values as shown, the corner frequency will be 20 kHz; however, the wide bandwidth of the AD712 permits a corner frequency as high as several hundred kilohertz. Equations for component selection are shown below. R1 = R2 = user selected (typical values: 10 k - 100 k)
C1 (in farads ) = 1.414 0.707 C2 = (2)( f cutoff )(R1) (2)( f cutoff )(R1)
C1 560pF +15V 0.1 F R1 20k R2 20k C2 280pF
REF 20.0 dBm OFFSET .0 Hz 10 dB/DIV RANGE 15.0 dBm 0 dB
TYPICAL BIFET
AD712
SPAN 10 000 000.0 Hz CENTER 5 000 000.0 Hz ST .8 SEC RBW 30 kHz VBW 30 kHz
VIN
1/2 AD712
0.1 F
VOUT
Figure 39.
-15V
Figure 38. Second Order Low Pass Filter
An important property of filters is their out-of-band rejection. The simple 20 kHz low pass filter shown in Figure 38, might be used to condition a signal contaminated with clock pulses or sampling glitches which have considerable energy content at high frequencies. The low output impedance and high bandwidth of the AD712 minimize high frequency feedthrough as shown in Figure 39. The upper trace is that of another low-cost BiFET op amp showing 17 dB more feedthrough at 5 MHz.
REV. B
-13-
AD712
+15V 0.1 F +15V 0.1 F VIN
A1 AD711
0.1 F
0.001 F
2800 4.9395E-15 A
6190 5.9276E-15 B
6490 5.9276E-15 C
6190 4.9395E-15 D
2800
A2 AD711
0.1 F
VOUT
4.99k
-15V 100k
*
*
*
*
0.001 F 124k
-15V 4.99k
*SEE TEXT
Figure 40. 9-Pole Chebychev Filter
9-POLE CHEBYCHEV FILTER
Figure 40 shows the AD712 and its dual counterpart, the AD711, as a 9-pole Chebychev filter using active frequency dependent negative resistors (FDNR). With a cutoff frequency of 50 kHz and better than 90 dB rejection, it may be used as an antialiasing filter for a 12-bit Data Acquisition System with 100 kHz throughput. As shown in Figure 40, the filter is comprised of four FDNRs (A, B, C, D) having values of 4.9395 10-15 and 5.9276 10-15 farad-seconds. Each FDNR active network provides a two-pole response; for a total of 8 poles. The 9th pole consists of a 0.001 F capacitor and a 124 k resistor at Pin 3 of amplifier A2. Figure 41 depicts the circuits for each FDNR with the proper selection of R. To achieve optimal performance, the 0.001 F capacitors must be selected for 1% or better matching and all resistors should have 1% or better tolerance.
+15V 0.1 F
REF 5.0 dBm 10 dB/DIV
MARKER 96 800.0 Hz RANGE -5.0 dBm -90 dBm
START.0 Hz RBW 300 Hz
VBW 30 Hz
STOP 200 000.0 Hz ST 69.6 SEC
Figure 42. High Frequency Response for 9-Pole Chebychev Filter
0.001 F
R
1/2 AD712
0.1 F
1/2 AD712
0.001 F -15V 1.0k
R:
24.9k 29.4k
FOR 4.9395E-15 FOR 5.9276E-15
4.99k
Figure 41. FDNR for 9-Pole Chebychev Filter
-14-
REV. B
AD712
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Mini-DIP (N-8)
0.390 (9.91)
8 5
Cerdip (Q-8)
0.005 (0.13) MIN 0.055 (1.35) MAX
5
0.250 0.310 (6.35) (7.87)
1 4
8
0.300 (7.62) REF 0.035 0.01 (0.890 0.25) 0.18 0.01 (4.57 0.76) SEATING PLANE 15 0 0.011 0.003 (0.204 0.081) 0.195 (4.95) 0.115 (2.93)
0.25R (0.64)
1 4
0.310 (7.87) 0.220 (5.59)
PIN 1 0.165 4.19 0.01 0.25
PIN 1 0.405 (10.29) MAX 0.200 (5.08) MAX 0.015 (0.38) 0.060 (1.52)
0.220 (5.59) 0.310 (7.87)
0.125 (3.18) MIN 0.018 0.003 0.100 0.033 (0.84) NOM (0.460 0.081) (2.54) TYP
0.150 (3.81) 0.125 (3.18) MIN 0.200 (5.08) 0.014 (0.36) 0.100 0.030 (0.76) SEATING PLANE 0.023 (0.58) (2.54) 0.070 (1.78) BSC
15 0
0.008 (0.20) 0.015 (0.38)
TO-99 (H-08A)
REFERENCE PLANE 0.185 (4.70) 0.165 (4.19) 0.500 (12.70) MIN
0.2440 (6.20) 0.2284 (5.80)
SOIC (R-8)
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
0.1574 (4.00) 0.1497 (3.80)
5
0.370 (9.40) 0.335 (8.50) 0.335 (8.50) 0.305 (7.75)
4 0.200 (5.1) TYP 0.100 (2.54) BSC 3 2 0.019 (0.48) 0.016 (0.41) 0.021 (0.53) 0.016 (0.41) BASE & SEATING PLANE 1
6 7 8
0.045 (1.1) 0.020 (0.51)
0.0098 (0.25) 0.0040 (0.10)
PIN 1
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
BOTTOM VIEW 0.034 (0.86) 0.028 (0.71) 45 BSC EQUALLY SPACED
0.040 (1.01) MAX INSULATION 0.05 (1.27) MAX
0.0500 0.020 (0.51) SEATING (1.27) 0.013 (0.33) PLANE BSC
0.0098 (0.25) 0.0075 (0.19)
8 0
0.050 (1.27) 0.016 (0.40)
REV. B
-15-
PRINTED IN U.S.A.
C1020c-1-4/98

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